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Petabit Switch Fabric Design

Lo, Jen-Hung
Cao, Yue
Zhou, Jingxue
Technical Report Identifier: EECS-2016-46
May 10, 2016

Abstract: Interconnection networks are used virtually in almost all digital systems that contain at least two components to connect be it CPU core, memory, or I/O device. As digital systems today continue to scale up, the interconnection network becomes one of the major bottleneck that limit the performance of the systems. Thus throughput and latency of the network are becoming more relevant than ever before when benchmarking a system’s performance. Thanks to the increase in pin bandwidth due to scaling of pin and wire density, the throughput of the network has been keeping pace with the rate at which systems are scaling. Furthermore, with high pin bandwidth a paradigm shift from low-radix wide-channel switch to high-radix narrow-channel switch can be seen. However, increasing the radix of a switch brings about various challenges as internal components such as crossbar switch and allocator scale at a faster rate than the radix. Our project, Petabit Switch Fabric Design, aims to sweep the design space of a high radix switch and draw a conclusion as to what the most optimal switch architecture is based on its performance metrics.