Flexible FFT Optimization and RTL Generation in the Chisel Hardware Design Language
Technical Report Identifier: EECS-2015-256
December 18, 2015
Abstract: Using hardware generators to produce components for modern SoCs enables rapid design space exploration. Embedding these hardware generators in a high-level programming language allows for simpler code, more expressive generators, and correspondingly better quality of results. This thesis describes the use of Chisel (Constructing Hardware in a Scala Embedded Language) to construct an FFT generator. The parametrized generator demonstrates automatic parameter-dependent test generation and seamless system integration. An analysis of FFT scheduling is performed to show how various mathematical properties of the Cooley-Tukey FFT decomposition may be exploited to simplify needed hardware while assuring conflict-free bank accesses for every operation. The resulting circuit throughput, energy, and area are shown to be better than or on par with other FFT generators.