A High-Throughput, Flexible LDPC Decoder for Multi-Gb/s Wireless Personal Area Networks
Technical Report Identifier: EECS-2010-177
December 22, 2010
Abstract: This work designs a low-power, high-throughput architecture compatible with any LDPC matrices containing groups of non-overlapping layers, which is a common matrix feature in emerging high-speed wireless standards. It gives a heuristic method for finding a near-optimal architecture and details the structure of each of the decoder's building blocks. To demonstrate the capabilities of proposed design, an entire decoder compatible with the 802.11ad wireless PAN/LAN standard was created in Simulink using Xilinx System Generator blocks and synthesized using Synopsys' Design Compiler. For the worst-case matrix, the decoder consumes 42mW at a throughput of 1.5Gb/s and 84mW at a throughput of 3Gb/s.