Design and Measurement of Parameter-Specific Ring Oscillators
Wang, Lynn Tao-Ning
Technical Report Identifier: EECS-2010-159
December 16, 2010
Abstract: Electronic monitoring utilizing process-specific Ring Oscillators (RO) is explored as a means of identifying, quantifying, and modeling sources of variation in circuit performance due to manufacturing and layout design parameters. This approach is motivated by the need to mitigate the increased impact of process variability on circuit performance in the scaling of CMOS. To reduce such impact, there is a need to monitor, analyze, and understand process variation in order to improve current design methodologies. This work contains the first measured silicon results for the utilization of parameter-specific modification of ring oscillator layouts to electronically monitor particular process variation. Design and testing for this work were made possible through the Berkeley Wireless Research Center. The working circuits were fabricated by ST Micro in a 45nm fabrication process that was under development. The design was based on a process design kit (PDK) provided by ST Micro. The lithography simulation was carried out using generic models in Mentor Graphics Calibre. Five systematic process effects were considered: etch, focus, misalignment, and capping layer and Shallow Trench Isolation (STI) stress. In all cases, inverter layouts were modified in order to increase sensitivity to a particular parameter within design rule constraints. Due to the dependence of layout geometries on parasitic capacitance, it was also necessary to pre-correct measurements for this effect. A total of 32 different inverter layouts were designed. This thesis demonstrates that ?parameter-specific ring oscillators? are suitable for multiple critical applications in quantifying systematic and random effects in the co-optimization of process development and circuit design. While parameter-specific RO monitors provide a permanent record of process effect, they are best used during process development and calibration, when less stringent design rules, no-OPC drop-ins, and programmed treatments can be accommodated, yielding inverter layouts with higher as well as directly verifiable sensitivity to process variation.