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Re-architecting DRAM with Monolithically Integrated Silicon Photonics

Beamer, Scott
Sun, Chen
Kwon, Yong-jin
Joshi, Ajay
Batten, Christopher
Stojanovic, Vladimir
Asanovic, Krste
Technical Report Identifier: EECS-2009-179
December 17, 2009

Abstract: Future manycore computing systems will only deliver increased performance if memory bandwidth improves also. Projected scaling of electrical DRAM architectures appears unlikely to suffice, being constrained by pin count and pin bandwidth, and by total chip power, including off-chip signaling, cross-chip interconnect, and bank access energy.

In this work, we redesign the main memory system using a proposed monolithically integrated silicon photonics technology and show that it provides a promising solution to all of these issues. Photonics can provide high aggregate pin-bandwidth density through dense wavelength-division multiplexing (DWDM). Photonic signaling also provides energy-efficient long-range communication, which we exploit to not only reduce chip-chip link power but also extend on to the DRAMs to reduce cross-chip interconnect power. To balance these large improvements in interconnect bandwidth and power, we must also improve the energy efficiency of the DRAM banks themselves, as we now require many concurrently accessed banks to support the available bandwidth. We explore decreasing the number of bits activated per bank to increase the banks' energy efficiency. Since DRAM chips are a very cost-sensitive commodity, we weigh these efficiency gains against any area overhead. Due to the immature nature of photonics technology, we explore a large design space to capture plausible designs for a range of different technology assumptions. Our most promising design point yields approximately a 10x improvement in power for the same throughput as a projected future electrical-only DRAM, with slightly reduced area.

Finally, we propose a new form of optical power guiding which increases the scalability of our memory architecture and allows for a single chip design to be used in both high capacity or high bandwidth memory configurations.