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EECS-2008-168.pdf
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0.35 um CMOS Process on Six-Inch Wafers, Baseline Report VI.

Authors:
Petho, Laszlo
Pongracz, Anita
Technical Report Identifier: EECS-2008-168
December 18, 2008
EECS-2008-168.pdf

Abstract: This report presents details of the fourth six-inch baseline run, CMOS180, where a moderately complex 0.35 um twin-well, silicided, LOCOS, Mix&Match photo process was implemented. This process was based on the first 0.35 um six-inch run, CMOS161. Different research circuits (IC/MEMS) were placed in the drop-in area: ring oscillators, a MEMS design, a hyperacuity chip and several different memory circuits.