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Collaborative Platform for DFM

Poppe, Wojciech Jacob
Technical Report Identifier: EECS-2007-175
December 20, 2007

Abstract: This dissertation addresses the two biggest challenges in Design for Manufacturing (DFM), how to inject process variations into design and how to identify and quantitatively characterize the main sources of transistor performance variation so that the information that is fed into design is accurate enough to make design tradeoff decisions effectively. To address these challenges the Collaborative Platform for DFM has been built in three main parts; the Parametric Yield Simulator, which is a scripted link between process simulation, non-rectangular device modeling, and circuit simulation, a process characterization strategy that leverages a large set of process sensitive electrical test structures for extracting process conditions, and a collaborative database that serves as the glue between simulation and experiment and facilitates high volume data analysis. The Parametric Yield Simulator (PYS) is built as a modular platform that links processing, currently lithography simulation, device modeling, and circuit analysis. This simulation flow is built around a non-rectangular transistor model that uses a set of channel position dependent slice lookup tables for fast model generation and translates a 2D geometrical gate shape into an equivalent 1D compact transistor model. The PYS can be wrapped with perl scripts to simulate layouts across the lithographic process window and hence be used for rapid prototyping of process sensitive test structures. In order to identify the main sources of threshold voltage variation and quantify their significance a multi-student testchip has been designed with over 15,000 individually probable transistors and test structures. All test structures are electrically probable and have various sensitivities to different process parameters. Most use a novel Enhanced Transistor Electrical CD Metrology (ETEC-M) that is based on an "enhanced" transistor that is 3X more sensitive to gate length variation than a standard transistor. In order to make sense of the high volumes of data, a relational database was built for data aggregation with structure that enables queries and flexibility to adapt as new attributes become necessary for data analysis. A high volume process extraction strategy used process sensitive and process insensitive test structures to identify a unique signature of each process parameter on the data, which it used to extract defocus and misalignment with sub-10nm accuracy. Some unintentionally sensitive designs where found to be 2X as sensitive to defocus as an isolated line. A second testchip, that has been manufactured in a short loop single layer experiment, demonstrated that using electrical open/short data from sets of structures can be used to extract defocus with sub-10nm accuracy. Sensitivities to different layout parameters were quantified in simulation and experiment. This thesis demonstrates how high volumes of electrical data from process specific test structures can be used to accurately characterize the main sources of transistor performance variation and enable more accurate DFM tools.