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Trap Architectures for Lisp Systems

Authors:
Johnson, Douglas
Technical Report Identifier: CSD-88-470
November 18, 1988
CSD-88-470.pdf

Abstract: Recent measurements of Lisp systems show a dramatic skewing of operation frequency. For example, small integer (fixnum) arithmetic dominates most programs, but other number types can occur on almost any operation. Likewise, few memory references trigger special banding for garbage collection, but nearly all memory operations could trigger such special handling. Systems like SPARC and SPUR have shown that small amounts of special hardware can significantly reduce the need for inline software checks by trapping when an unusual condition is detected.

A system's trapping architecture now becomes key to performance. In most systems, the trap architecture is intended to handle errors (e.g., address faults) or conditions requiring large amounts of processing (e.g., page faults). The requirements for Lisp traps are quite different. In particular, the trap frequency is higher, processing time per trap is shorter, and most need to be handled in the user's address space and context.

This paper looks at these requirements, evaluates current trap architectures, and proposes enhancements for meeting those requirements. These enhancements increase performance for Lisp 9%-32% at cost of about 1.4% more CPU logic.