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Design and Implementation of RISC I

Sequin, C.H.
Patterson, D.A.
Technical Report Identifier: CSD-82-106
October 1982

Abstract: The Reduced Instruction Set Computer (RISC) is an architecture particularly well suited for implementation as a single-chip VLSI computer. It demonstrates that by a judicious choice of a small set of instructions and the design of a corresponding micro-architecture, one can obtain a machine with high throughput. The limited number of instructions and addressing modes leads to a small control section and to a short machine cycle time. Such a machine also requires a much smaller layout effort and thus leads to a shorter design cycle.

Such a RISC architecture has been implemented at U. C. Berkeley as part of a four quarter sequence of graduate courses in which students propose and evaluate architectural ideas, design LSI components, integrate those components into a VLSI chip, and finally test the actual chip. The CAD and testing environment in which this chip was created is also described.