Exploiting Prediction to Reduce Power on Buses
Abstract: We explore the possibility of reducing energy consumed by on-chip buses via stateful and stateless coding techniques. We explore the design of a number of simple coding schemes and simulate them using a modified SimpleScalar simulator and SPEC benchmarks. We show an average of 36% savings in transitions on internal buses such as the reorder buffer and register file. To quantify actual power savings, we design a simple dictionary based encoder/decoder circuit in a 0.13-micron process, extract it as a netlist, and simulate its behavior under SPICE. Utilizing a realistic wire model with repeaters, we show that we can break even at median length scales of less than 11.5mm at 0.13 microns and project a break-even point of 2.7mm for a larger design at 0.07 microns.